Wafer Fab

The basis of modern production of electronics products is the manufacture of silicon chips on the wafer fab. The level of technical characteristics and economic indicators of both the IC itself and electronics products based on them are determined by the level of wafer fab technology.

JSC "ZNTÑ" has a high-tech wafer fab with a complete set of equipment starting from tools for marking of the blank wafers to the final wafer testing processes, packaging and measuring. The technological line tools are  installed by the world's leading manufacturers, such as the English company "SPTS", the Japanese "ULVAC", the USA "Teradyne" and others.

The reliability and quality of the processes guarantee by availability of a comprehensive engineering infrastructure and debugged service procedures.

Wafer fab JSC "ZNTC" has a full set of equipment and proven technological processes for creating CMOS integrated circuits and MEMS.

The main parameters of the production line are follows:

- diameter of the processed wafers - 6 inches (150 mm),

- a project for expanding production and setting up technology on wafers of 8 inches (200 mm) is being implemented,

- area of ​​clean rooms (clean room) - 850 sq. m. with plans for expansion up to 1500 sq.m,

- cleanliness classes in the clean room - 10, 100, in the technical service area - 10,000,

- the design rule (lithography resolution) 0.6 μm and 0.25 μm,

- in process the project 200 mm wafers with a photolithography resolution level of 130 nm,

- state-of-the art engineering infrastructure.

Characteristics of wafer fab production shops

At the facilities of wafer fab for nano- and microsystem technology products of JSC ZNTC IC chips are manufactured, a full range of services is provided for the development and production of microelectronic products.

 Photolithography, process area 54 m2, clean room class -100.

 Wet chemical treatment, process area 70 m2, clean room class -100

 Diffusion, process area 37 m2, clean room class -100

 Etching, process area 30 m2, clean room class -100

 Vacuum coating (PVD), process area 30 m2, clean room class -100

Implantation, process area 40 m2, clean room class -100

At the photolithography section, a complex of processes of forming a photoresist mask on silicon wafers is performed, including washing the wafers, applying (spin and aerosol) a photoresist layer, drying, aligning and exposing, developing and hardening.

Equipment of contact photolithography allow to carry out the process of contact alignment and exposure (there is a possibility of double-sided alignment) of silicon wafers up to 150 mm in diameter. The minimum size of the formed topology element on a silicon wafer is 600 nm.

Tool of projection lithography ASML PAS 5500 / 300C for 250 nm technology is used on the principle of a closed cycle in combination with automated equipment for applying and developing photoresist - ACT-8.

To control the linear dimensions and alignment accuracy, an automatic high-magnification microscope MueTec is used with possibility of automatic sorting out. To control the defectiveness, a complete mapping of the wafer is carried out with the classification of defects by size. The time for automatic rejection of a 150 mm wafer does not exceed 30 seconds.

On the ​​wet chemical treatment section etching and chemical process of silicon wafers surface cleaning are carried out. Modern equipment provides automatic supply of chemical solutions to tools for chemical etching and surface cleaning of silicon wafers. Chemical etching tools perform operations of wet etching of layers of metals and dielectrics, anisotropic etching of silicon, refreshing (cleaning) the silicon surface from natural silicon oxide, cleaning the surface of substrates from particles and metal ions for further subsequent technological operations. The site has a separate area for washing quartz and metal holders, as well as polypropylene containers in separate baths.

Diffusion / deposition section. Thermal atmospheric ovens allow oxidation processes in dry and wet oxygen, as well as processes of phosphorus diffusion and low-temperature annealing.

The LPCVD and PECVD deposition tools allow the deposition of various dielectric (SiO2, Si3N4, SiOxNy, SiO2 TEOS, FSS, BFSS, etc.) and polysilicon layers. The uniformity of the thickness of the applied films over the wafer area 150 mm is 1σ ≤3%.

Fast-heat treatment tools allow fast annealing processes to activate implanted impurities, oxidation and nitridation of the silicon surface.

The atomic-layer deposition tool allows to deposition of thin monatomic conductive and dielectric layers with a very high conformal filling of the surface relief of the samples (typical layer thicknesses 1-500 À0  ). It is possible to set up unique technological processes using various types of metallization in accordance with the technical spec.

Plasma etching section is equipped with cluster-type equipment, allowing to carry out especially critical processes of silicon etching in an ultrapure plasma environment. 

The STS VPX tool is used for aluminum metallization layers etching, as well as post-corrosion treatment and removal of the photoresist mask. The STS CPX tool is used for etching dielectric layers of silicon nitride, silicon oxide, FSS, etc.), as well as silicon and polysilicon. It provides an ultra-deep silicon etching process, the so-called BOSCH process, which is one of the key steps in the MEMS formation technology.

Plasma stripping tools allow us for quick and efficiently remove of the photoresist mask. It provides the ability to carry out charge-free removal of the photoresist at the critical stages of the route for the manufacture of microcircuit chips.

The ion etching tool makes it possible to form metallization systems based on layers of platinum, iron, chromium, nickel, etc. Etching uniformity over an area of wafer 150mm is 1σ ≤3.5%.

The thin film coating section equipped with several vacuum coaters, where PVD DC coating method of conductive layers, including magnetoresistive and precious metals, as well as dielectric SiO2 and other layers by PVD RF methods, is carried out.

Uniformity of the applied film thickness over the wafer area of diameter 150 mm 1σ ≤5%; for magnetoresistive films, the thickness uniformity over the same area is 1σ ≤ 1%.

Ion doping section, where the operations of implantation of boron, phosphorus, arsenic, argon, and nitrogen ions are carried out at medium currents with energies from 10 to 200 keV. Double / triple ion implantation is possible. Implantation angle from 0˚ to 45˚. Doses: 1 × 1011àò/ñì2    to 1 × 1018 at / sm2. Dose inhomogeneity over the entire implantation area and from wafer to wafer is 1σ ≤1%.

Atomic Layer Deposition (ALD) technology is one of the important processes in wafer production used to deposit thin monoatomic conductive and dielectric layers with very high conformal filling of the surface relief of samples.Atomic Layer Deposition (ATL) is a surface-controlled and self-limiting gas-phase film deposition method that produces thin coatings that are 100% uniform and conformable, free from defects, cracks, and microchannels. This method allows the deposition of films both on surfaces with large areas and on substrates with relief features at nano scales (for example, deep grooves and slots) with an ultra-high aspect ratio and porous samples with high tortuosity of channels).

The ALD method allows the deposition of nanolayers of metal oxides, nitrides, sulfides, fluorides and metallic (including noble metals) coatings, nanolaminates, stepped layers, mixed oxide and doped thin films.